The present invention relates to a semiconductor memory device and, more particularly, to a semiconductor memory device employing, as a scheme of detecting data in a nonvolatile memory cell, a scheme of detecting the potential depending on the relationship in amplitude between the current for charging a bit line and the cell current and, more particularly, to a sense amplifier therefor.
This application is based on Japanese Patent Application No. 9-27748, filed Feb. 12, 1997 and Japanese Patent Application No. 9-333816, filed Dec. 4, 1997, the content of which is incorporated herein by reference.
An example of such a semiconductor memory device is a nonvolatile semiconductor memory device such as a NAND EEPROM. An EEPROM has advantages including nonvolatility: cell data is not erased even upon turning off the power supply, and strong demand therefor has arisen in recent years. Especially, a flash memory in which data in plural cells can be erased simultaneously and memory cell is constituted by one MOSFET is expected to, e.g., replace a large-capacity magnetic disk. A NAND EEPROM is known as an EEPROM allowing high integration.
FIG. 1 shows the entire arrangement of a simultaneous-erasable NAND EEPROM. This EEPROM comprises a memory cell array (NAND cell array) 11 in which a plurality of NAND memory cells are arrayed in a matrix, a number of bit lines BL extend in the vertical direction, and a number of word lines WL extend in the horizontal direction, a row decoder 12 for selectively driving the word lines WL of the memory cell array 11 on the basis of an address input from an external unit(not shown), a sense amplifier (and write data latch circuit) 13 connected to the bit line BL of the memory cell array 11, a column gate 15 connected to the sense amplifier 13, a column decoder 14 for controlling the column gate 15 on the basis of the address input from the external unit and selecting corresponding bit line BL and sense amplifier 13, an I/O buffer 18 connected to the column gates 15, a voltage step-up circuit 16 for supplying a high voltage necessary for a write or erase operation, and a control circuit 17 serving as an interface between the chip and the external unit.
The row decoder 12 selectively drives the plurality of word lines WL on the basis of an address signal in the data write, erase, or read mode. A predetermined voltage is applied from the voltage step-up circuit 16 to a word line driver (not shown) in the row decoder 12.
A bit line driver (not shown) is also arranged to selectively apply predetermined voltages to the bit lines BL in the data write, erase, or read mode.
FIG. 2A shows a NAND memory cell in the memory cell array 11 shown in FIG. 1.
A plurality of memory cell MOSFETs M1 to M8 each constituted by an N-channel MOSFET having a floating gate and control gate are connected in series. The drain of the MOSFET at one end of this series circuit is connected to the bit line BL through a selection gate NMOSFET Q1 while the source of the MOSFET at the other end is connected to a common source line CS through a selection gate NMOSFET Q2.
The MOSFETs are formed on the same well W. The control electrodes of the memory cells M1 to M8 are respectively connected to word lines WL1 to WL8 continuously arranged in the row direction. The control electrode of the selection MOSFET Q1 is connected to a selection line SL1, and the control electrode of the selection MOSFET Q2 is connected to a selection line SL2.
Each of the memory cell MOSFETs M1 to M8 has a threshold value corresponding to data to be stored. In the NAND flash memory, "1" data storing state (erase state) is defined as a state wherein the memory cell MOSFET is of a depletion type (D type), and the "0" data storing state (write state) is defined as a state wherein the memory cell MOSFET is of an enhancement type (E type). An operation of shifting the threshold value of the memory cell MOSFET which is storing data of level "1" in the positive direction to store data of level "0" is called a "write operation". An operation of shifting the threshold value of the memory cell MOSFET which is storing data of level "0" in the negative direction to store data of level "1" is called an "erase operation".
FIG. 2B shows the distribution of threshold values of memory cell MOSFETs of the NAND cell.
The data write, erase, and read operations of this NAND cell will be described next.
A data write in the NAND cell is sequentially performed from the memory cell MOSFET far from the bit line BL. For an N-channel memory cell MOSFET, a voltage of, e.g., 0V or an intermediate voltage V.sub.m (almost an intermediate voltage between a write voltage V.sub.pp and the ground potential) is applied to the bit line BL depending on whether data of level "0" is to be written (the threshold value is to be shifted) or data of level "1" is to be stored (the threshold value is not to be shifted).
The write voltage V.sub.pp boosted and capable of obtaining a necessary electric field for shifting the threshold value of the cell is applied to the control gate of a selected memory cell MOSFET. The intermediate voltage V.sub.m necessary for transferring the voltage of the bit line BL to the selected memory cell MOSFET without shifting the threshold value of the cell is applied to the gate of the selection MOSFET and control gates of nonselected memory cell MOSFETs. A voltage of 0V is applied to the selection line SL2, the well, and the common source line CS.
As a result, all the MOSFETs from the selection MOSFET Q1 to the memory cell M8 are turned on. The voltage of the bit line BL is transferred to the drain of the selected memory cell MOSFET through the nonselected memory cell MOSFETs. In this case, a drop in threshold of the memory cell MOSFET need not be taken into consideration because data is normally erased before the write in the memory cell MOSFET, and the threshold value of the memory cell MOSFET does not drop.
When data of level "0" is to be written (when a voltage of 0V is applied to the bit line BL), a strong electric field is applied across the floating gate, channel, and drain of the selected memory cell MOSFET. Electrons are tunnel-injected into the floating gate, and the threshold value shifts in the positive direction. When data of level "1" is to be written (when the intermediate voltage V.sub.m is applied to the bit line BL), the intermediate voltage V.sub.m is applied across the floating gate, channel, and drain of the selected memory cell MOSFET. This suppresses the shift in threshold value in the positive direction, so the threshold value does not change. The intermediate voltage V.sub.m having a certain value, which is applied to the bit line BL to prevent shift in threshold value of the cell, is called a write-inhibiting voltage.
A data erase from the NAND cell is simultaneously performed for all memory cell MOSFETs in the NAND cell. More specifically, the bit line BL is opened, a voltage of 0V is applied to the control gates of all memory cell MOSFETs, a boosted erase voltage V.sub.e necessary for erasing cell data is applied to the p-type well and n-type substrate. A voltage (e.g., the same potential as the well) at which the gates of the selection MOSFETs Q1 and Q2 are not destructed is applied to the selection lines SL1 and SL2. The same potential as the well (or an open state) is applied to the common source line CS. With this operation, electrons in the floating gates of all memory cell MOSFETs are discharged to the p-type well through the gate insulating film, so the threshold value shifts in the negative direction.
A data read from the NAND cell is performed in the following manner. A reference voltage of 0V is applied to the control gate of the selected memory cell MOSFET, a power supply voltage V.sub.cc is applied to the control gates of the remaining memory cell MOSFETs and the gates of the selection MOSFETs, and a voltage of 0V is applied to the well and the common source line CS. The sense amplifier detects whether a current flows to the selected memory cell MOSFET.
In this case, all MOSFETs (including nonselected memory cells) other than the selected memory cell are turned on. When data of level "0" is stored in the selected memory cell MOSFET, this memory cell is turned off, so the potential of the bit line does not change. When data of level "1" is stored in the selected memory cell MOSFET, the memory cell is turned on to discharge the electrons on the bit line, so the bit potential lowers.
FIG. 3 shows a circuit corresponding to some bit lines BL (e.g., five bit lines) in the memory cell array 11 shown in FIG. 1.
In this circuit, a NAND memory cell MC is connected to each bit line BL, a sense amplifier S/A is connected to each bit line BL, and a data bus is connected to the sense amplifiers S/A. Control signals or voltages Latch, CMout, Load, DCB, BLSHF are supplied to each sense amplifier S/A.
The data read operation of the circuit shown in FIG. 3 will be described. First, each bit line BL is precharged to the power supply potential, a specific word line WLi (i=1, 2, . . . , 8) is selected, and each sense amplifier S/A senses and amplifies whether the corresponding bit line BL is discharged or not (stores the potential in the precharged state without being discharged) in accordance with the data of the plurality of memory cell MOSFETs M1 to M8 connected to the specific word line.
FIG. 4 shows a conventional example of the sense amplifier S/A shown in FIG. 3.
This sense amplifier comprises a constant current source P-channel MOSFET M1 for charging the bit line BL for a predetermined period on the basis of the precharge control signal CMout, a bit line potential clamp N-channel MOSFET M5 inserted in series with the bit line BL and having a gate to which the control voltage BLSHF is applied, a latch circuit LT for latching memory cell data read out to a bit line potential sense node N3 between the P-channel MOSFET M1 and the N-channel MOSFET M5, an N-channel MOSFET M2 for discharging charges from bit line potential sense node N3 for a predetermined period on the basis of the discharge control signal DCB, a bit line potential sense NMOSFET M3 connected between a first latch node N1 of the latch circuit LT and the ground node and having a gate connected to the bit line potential sense node N3, a latch circuit forcible inversion control NMOSFET M4 connected in series with the NMOSFET M3 between the first latch node N1 of the latch circuit LT and the ground node and turned on in accordance with the control signal Latch supplied to the gate for a predetermined period, and a sense amplifier reset/transfer gate NMOSFET M6 inserted between the bit line potential sense node N3 and a second latch node N2 of the latch circuit LT and gate-driven in accordance with the control signal Load.
The latch circuit LT comprises a flip-flop circuit (latch circuit) constituted by cross-connecting (inversely parallelly connecting) the input nodes and output nodes of a first CMOSFET inverter IV1 and a second CMOSFET inverter IV2.
In this case, the input node (first latch node N1) of the first CMOSFET inverter IV1 is connected to the forcible inversion control NMOSFET M4 as a forcible inversion input node. The input node (second latch node N2) of the second CMOSFET inverter IV2 is connected to the sense amplifier reset NMOSFET M6 and also connected to the data bus as a reset node.
The read, erase, and write operations of the sense amplifier shown in FIG. 4 will be described next.
In the read mode of the EEPROM, the MOSFETs M2 and M6 are turned on for a predetermined period to reset the latch circuit LT, so the node N2 is set at "L" level, and the node N1 is set at "H" level. After this, the bit line BL is charged with the constant current from the MOSFET M1 and discharged to flow a cell current I.sub.cell generated on the basis of the threshold state of the memory cell MOSFET while keeping the constant current flowing. After a predetermined time, the MOSFET M4 is turned on.
When data of level "1" is read out from the NAND cell to the bit line BL, the bit line potential lowers because the cell current I.sub.cell flows. The MOSFET M3 is turned off, and the node N1 is kept at "H" level in the reset state of the latch circuit LT. Inversely, when data of level "0" is read out from the NAND cell to the bit line BL, the bit line potential is kept at "H" level because no cell current I.sub.cell flows. The MOSFET M3 is turned on to forcibly invert data stored in the latch circuit LT, so the node N1 is set at "L" level, and the node N2 is set at "H" level. The data of the node N2 of the latch circuit LT corresponding to the selected column is read out to the data bus.
When data is to be erased from the EEPROM, the sense amplifier is used for a verify read operation. At this time, the sense amplifier operates in the same manner as in the read mode. If data in the memory cell MOSFET has been erased (in case of data of level "1"), the node N1 is set at "H" level, and the node N2 is set at "L" level. If data in the memory cell MOSFET has not been erased (in case of data of level "0"), the node N1 is set at "L" level, and the node N2 is set at "H" level. On the basis of this data, if any one of the nodes N2 of all sense amplifiers S/A operating simultaneously is set at "H" level, the erase is incomplete, and a signal for erase is output to perform erase again.
In the write mode of the EEPROM, write/write-inhibiting data is input, and data is input from the data bus to the node N2 of the latch circuit LT corresponding to the selected column. When data of level "0" is input, the node N2 is set at "L" level. When data of level "1" is input, the node N2 is set at "H" level. Upon turning on the MOSFET M6, the data of the node N2 is transferred to the bit line BL through the MOSFET M6. In the write mode, the channel in the selected NAND cell is boosted to the intermediate potential. Therefore, when data of "L" level is supplied to the bit line BL, the data is written in the cell. When data of "H" level is applied to the bit line BL, no data is written.
To realize highly reliable EEPROM capable of operating at a high speed, the threshold distribution of the memory cell MOSFETs after being written must be narrow. As described above, every time data is written, the written data is read out (verify read) and compared with data to be written. If the writing is insufficient, the write operation is continued. Upon confirming that the written data agrees with that to be written, the write operation is ended.
In such a verify read mode, the latch circuit LT is not reset, and the reading is performed while keeping the written data left in the sense amplifier. This read operation is the same as in the read mode except the absence of reset.
Therefore, the node N2 of the latch circuit LT corresponding to a cell not to be written or a completely written cell is set at "H" level. The node N2 of the latch circuit LT corresponding to an incompletely written cell is set at "L" level. When data of the nodes N2 are directly used to perform the write operation again, data can be written in only incompletely written cells.
In the read mode, a voltage of 0V is applied to the selected word line. In the verify read mode, however, a verify voltage V.sub.pvf (&gt;0V) is applied to the selected word line. Data is rewritten in memory cell MOSFETs each having a threshold value from 0V to V.sub.pvf, and the write operation is repeated until the minimum value of the write threshold distribution is equal to or larger than the verify voltage V.sub.pvf. With this arrangement, a sufficient margin for the write variation to the read voltage is ensured.
As described above, in the read mode, the sense amplifier shown in FIG. 4 is discharged while flowing the cell current I.sub.cell with keeping the flow of the constant current by the MOSFET M1. This scheme can shorten the read time as compared to a scheme (e.g., the bit line precharge/discharge scheme) of charging the bit line to a floating state and then flowing the cell current to sense the decrease in bit line potential.
However, in the sense amplifier shown in FIG. 4, the cell current (constant current) from the MOSFET M1 always flows in the read mode, so the ground potential floats depending on the data pattern stored in the cell. More specifically, when the constant current flows to a parasitic resistance r between the memory cell MC and ground to drop the voltage, the ground terminal (source of the selection MOSFET SL2) of the memory cell MC slightly floats from the ground potential. Especially, when data in all cells have been erased, a large constant current flows into all the bit lines BL. As a result, the source-side potential of the NAND memory cell MC (e.g., ground potential) tends to float because of the voltage drop of the resistance component of the common source line CS using a diffusion layer at a source-side terminal of the NAND cell, so the cell current decreases. In addition, floating of the ground potential generates a back bias effect, so the apparent threshold value of the cell becomes high.
The write/erase operation of the EEPROM is slower than that of, e.g., a DRAM, and some EEPROMs employ a page write scheme or a page read scheme to realize a high-speed write/read.
In the page write scheme, data to be written are written simultaneously from a plurality of column lines (bit lines) in a plurality of memory cells connected to one row line (word line) (written in units of pages). In the page read scheme, data stored in a plurality of memory cells connected to one row line are simultaneously read out to a plurality of column lines and sense-amplified (read out in units of pages).
For this EEPROM, assuming the verify operation based on the page write scheme, problems due to floating of potential of the common source line CS (to be referred to as floating of the ground potential hereinafter) will be described below.
For a page size of, e.g., 512 columns, assume that all cells not subjected to data writing have been erased, and that one memory cell MOSFET has a very high write speed. Assume that, in the first writing, about 0 to 1V is written in the cell with the highest write speed while each of the remaining cells has a threshold voltage of 0V or less.
When a verify read is performed in this state, a current flows to cells of the 511 columns except the cell with the highest write speed, so a voltage drop occurs due to the parasitic resistance component r of the interconnection (e.g., the diffusion layer) on the source side of the NAND cells, so the ground potential floats.
Since the cell current decreases due to floating of the ground potential, the cell with the highest write speed appears to be sufficiently written (i.e., the threshold voltage is higher than the actual threshold voltage) although data written in the cell is insufficiently in fact. It is consequently determined upon verification that the write in the cell with the highest write speed is complete.
However, in a page read after completion of writing in all cells, the writing has been ended for most cells, and no cell current flows, so floating of the ground potential is minimum.
In the read operation when the floating of the ground potential is minimum, the cell current is apparently more likely to flow to the cell with the highest write speed than in verification after the first writing. For this reason, the writing in the cell with the highest write speed may be insufficient to result in a write failure although it is determined that the writing is complete. This also poses the problem of reliability.
In summary, in the conventional semiconductor memory device which employs, as a sense scheme, a scheme of discharging the bit lines and sensing the cell current while charging the bit lines in reading out data from the nonvolatile memory cells, and as a read scheme, a scheme of simultaneously reading out data stored in the plurality of memory cells connected to the plurality of bit lines and detecting the data, and also has a verify mode after the writing operation in the memory cells, when a memory cell having a high write speed is included in the plurality of memory cells, the potential of the common source line of the plurality of memory cells floats in the verify operation after the write to cause a write failure.